Digital Verification Engineer(m/f/d)

Location: Wien

Our Digital Design department contributes ASIC and FPGA systems for precise real-time control (with nanoseconds accuracy) and high-speed data transmission that meet very demanding requirements. This team is responsible for system-level verification of ASIC/FPGA designs in UVM/SystemVerilog.

Responsibilities:

  • Create and maintain verification plans for complex ASICs/FPGAs
  • Develop functional verification environments in UVM/SystemVerilog
  • Set up and run regression to attain the verification goals
  • Analyze code and functional coverage

Qualifications:

  • University degree in Electrical Engineering / Computer Engineering / Embedded Systems or other comparable education
  • 3+ years of industry experience in verification of ASIC/FPGA designs
  • Strong analytical and debugging skills
  • Fluent English skills with German skills as a plus
  • Experience in developing UVM based - SystemVerilog test benches is desired
  • Experience with assertions (OVL/SVA) is preferred
  • Good knowledge of scripting languages like Shell/TCL/Python/Perl is a plus

We offer:

  • Growing High-Tech Company with headquarter in Austria and international branches (Taiwan, Korea, USA)
  • Top equipped workplace (modern office, laptop, height adjustable desk).
  • A culture welcoming high engagement
  • A motivated team with a flat hierarchy and short lines of communication
  • An annual gross salary starting from EUR 50.000,-- depending on your qualification and professional experience

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