Junior Digital Verification Engineer(m/f/d)

Location: Wien


  • Create and maintain verification plans for complex ASICs/FPGAs
  • Develop functional verification environments in UVM/SystemVerilog
  • Set up and run regression to attain the verification goals
  • Analyze code and functional coverage


  • University degree in Electrical Engineering / Computer Engineering / Embedded Systems or other comparable education
  • Strong analytical and debugging skills
  • Good communication skills
  • Enthusiastic and willingness to learn and improve
  • Results-oriented attitude
  • Fluent English skills with German skills as a plus
  • Knowledge of hardware description languages - Verilog/SV/VHDL - is a plus
  • Knowledge of scripting languages like Shell/TCL/Python/Perl is a plus
  • Knowledge of Object Oriented Programming concepts is a plus

We offer:

  • High-Tech Company with headquarter in Austria and international branches (Taiwan, Korea, USA)
  • Responsibility and opportunity to perform independent tasks in a dynamic company in an intercultural environment
  • Excellent professional and personal development opportunities in an international company
  • Top equipped workplaces (modern office, laptop, height adjustable desk)
  • A young and motivated team with short communication channels.
  • An annual gross salary starting from EUR 42.000,- depending on your qualification and professional experience

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