Senior Verification Engineer(m/w/d)

Location: Wien

Our Digital Design department contributes ASIC and FPGA systems for precise real-time control (with nanoseconds accuracy) and high-speed data transmission that meet very demanding requirements. This team is responsible for system-level verification of ASIC/FPGA designs in UVM/SystemVerilog.

Responsibilities:

  • Create and maintain verification plans for complex ASICs/FPGAs
  • Develop verification environments in UVM/SystemVerilog
  • Set up and maintain regression infrastructure to attain the verification goals for RTL and netlist
  • Analyze code and functional coverage reports
  • Participate in technical peer-reviews
  • Improve verification infrastructure and establish best practices
  • Mentor junior verification engineers
  • Work in close collaboration with the design team to ensure high quality verification

Qualifications:

  • University degree in Electrical Engineering / Computer Engineering / Embedded Systems or other comparable education
  • 5+ years of industry experience in verification of ASIC/FPGA designs
  • Strong understanding of Object Oriented Programming concepts
  • Hands-on experience in verification environment architecture definitions and development.
  • Extensive experience in developing UVM based - SystemVerilog testbenches
  • Experience with assertions (OVL/SVA)
  • Good knowledge of scripting languages like Shell/TCL/Python/Perl
  • Strong analytical and debugging skills
  • Fluent English skills with German skills as a plus

We offer:

  • A young and motivated intercultural team with short communication channels
  • Excellent professional and personal development opportunities
  • Annual gross salary: from EUR 54.000,-- open to negotiation depending on qualifications and experience

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